|
Milestone |
Target |
Actual |
x |
Complete project proposal |
2007.02.07 |
2007.02.07 |
x |
Complete requirements document |
2007.02.28 |
2007.02.28 |
x |
Design and test basic low-level components (in VHDL) |
2007.04.06 |
2007.04.06 |
x |
Design and test register file |
2007.04.09 |
2007.04.10 |
x |
Complete functional design document |
2007.04.11 |
2007.04.11 |
x |
Design and test ALU |
2007.04.11 |
2007.04.14 |
x |
Design and test RAM |
2007.04.11 |
2007.04.22 |
x |
Design and test instruction decoder |
2007.04.13 |
2007.04.22 |
x |
Design and test stack module |
2007.04.13 |
2007.04.18 |
x |
Design and test comparator |
2007.04.13 |
2007.04.20 |
x |
Design and test Short Bus interface |
2007.04.13 |
2007.04.22 |
x |
Successfully integrate core CPU and Short Bus |
2007.04.13 |
2007.04.24 |
x |
Synthesize VHDL codebase successfully (with Xilinx ISE) |
2007.04.16 |
2007.04.24 |
x |
Write assembly to machine code compiler for core CPU |
2007.04.16 |
2007.04.25 |
|
Adapt 10/100Mbps Ethernet controller to interface with Short Bus |
2007.04.20 |
|
|
Write assembly program with core CPU successfully responding to physical I/O |
2007.04.20 |
|
|
Modify assembly program to respond to ethernet I/O |
2007.04.21 |
|
|
Implement impulse filter in assembly program |
2007.04.23 |
|
|
Build physical components |
2007.04.28 |
|
|
Integrate project; completion of project |
2007.04.28 |
|